Generally, a GaAs Schottky gate type field effect transistor (hereinafter referred to as "GaAs-MESFET") has a high electron mobility and exhibits a superior characteristics as a super high frequency element or a super high speed element. FIG. 6(a) shows an equivalent circuit of a general GaAs-MESFET and FIG. 6(b) shows a construction of a GaAs-MESFET and circuit elements included in this structure.
In FIG. 6(a) and 6(b) reference numerals 15, 16, and 17 designate a source electrode, a gate electrode, and a drain electrode, respectively. When a low noise FET is adopted as a basic FET, the relationship between the equivalent circuit and the minimum noise figure (F.sub.0) is: ##EQU1## Herein, k is a constant
f is the frequency of operation
Cgs is the gate to source electrode capacitance
Rs is the source resistance
Rg is the gate resistance
gm is the transconductance.
The minimum noise figure is a ratio of the input side S/N (Signal to Noise ratio) to the output side S/N, and the smaller this minimum noise figure is, the better the device efficiency is. It is deduced from formula (1) that to improve the minimum noise figure, the source/gate capacitance Cgs, the source resistance Rs, and the gate resistance Rg should be reduced, and the transconductance gm should be increased.
FIG. 7 shows a cross-section of a field effect transistor having a refractory metal self-aligned gate according to the prior art. This prior art FET starts with a semi-insulating GaAs substrate 1. An active layer 2 is produced at a surface region of the semi-insulating GaAs substrate 1 by ion implantation. A refractory metal silicide gate 3 which produces a Schottky junction with the GaAs substrate 1 is produced on the active layer 2. A source region 4 and a drain region 5 of high doping concentration are produced by ion implantation using the refractory metal silicide gate 3 as a mask. A source electrode 6 and a drain electrode 7 are produced at the surface of the source region 4 and the drain region 5, respectively, in ohmic contact therewith.
The production method of the FET of FIG. 7 will be described with reference to FIGS. 8(a) to (d).
First of all, an active layer 2 is produced at a surface region of the semi-insulating GaAs substrate 1 by ion implantation, a refractory metal silicide layer 3 is applied to the entire surface of the wafer, and a gate pattern is produced using photoresist 9 (FIG. 8(a)).
Next, the refractory metal silicide layer 3 is isotropically etched by reactive ion etching (hereinafter referred to as "RIE") using the photoresist film 9 patterned as described above as a mask, thereby producing a gate electrode 3 (FIG. 8(b)).
Thereafter, ion implantation is conducted using the refractory metal silicide layer 3 as a mask, followed by annealing to produce high concentration doping layers which will become a source region 4 and a drain region 5 (FIG. 8(c)).
Thereafter, a source electrode 6 and a drain electrode 7 are produced by evaporation and lift-off, thereby completing the FET of FIG. 7 (FIG. 8(d)).
In the prior art FET shown in FIG. 7, the drain region 5 and the refractory metal silicide gate 3 are adjacent to each other. This arrangement lowers the breakdown voltage between the gate and drain, reduces reliability, and makes it difficult to apply the FETs to high power analogue integrated circuits (ICs).
In view of such problems, a device of following structure is proposed. FIG. 9 shows an FET disclosed in Japanese Patent Publication No. 62-86870. FIGS. 10(i a) to 10(f) show major production process steps for producing the FET of FIG. 9. In these figures, the same reference numerals designate the same elements as those shown in FIG. 7.
The production method of the device of FIG. 9 will be described with reference to FIG. 10.
Silicon ions are implanted into a semi-insulating GaAs substrate 1 by ion implantation, thereby producing an active layer 2 which becomes a channel region (FIG. 10(a)).
Then, a refractory metal silicide 3 is vacuum evaporated on the surface of the active layer 2, an insulating film 8 comprising SiO.sub.2 is deposited on the refractory metal silicide layer 3 by a chemical vapor deposition (CVD) method, and the refractory metal silicide layer 3 and the insulator film 8 are given a length corresponding to the source-drain distance by conventional photolithography processes (FIG. 10(b)).
Next, the source sides of the refractory metal silicide layer 3 and the insulator film 8 are covered by photoresist 9, and a portion of the insulator film 8 on the refractory metal silicide layer 3 is removed with using the photoresist 9 as a mask.
Next, the photoresist 9 is removed and silicon ions are injected utilizing ion implantation (FIG. 10(d)).
Next, the refractory metal silicide layer 3 is etched using the insulator film 8 as a mask, thereby to produce a gate electrode 3. A source region 4 and a drain region 5 are produced by thermal processing in an arsenic ambient (FIG. 10(e)).
Next, ohmic electrodes comprising Au-Ge are produced on the source region 4 and the drain region 5 utilizing conventional photolithography processes, thereby producing a source electrode 6 and a drain electrode 7. The insulator film 8 is removed to complete the FET of FIG. 9 (FIG. 10(f)).
In the FET having the structure shown in FIG. 9, a predetermined distance is provided between the electrode 3 comprising a refractory metal silicide and the drain region 5, which results in a high gate to drain breakdown voltage.
In the FET shown in FIGS. 7 and 9, however, source region 4 is produced adjacent the refractory metal silicide gate 3, thereby resulting in the likelihood of short-circuiting between the source region 4 and the gate electrode 3. In addition thereto, since the gate electrode 3 is provided adjacent the source region 4, impurities implanted into the source region 4 are likely to intrude into the region below the gate electrode 3 by diffusing in a transverse direction during the annealing process for activating impurities implanted into the source region 4. This impurity diffusion shrinks the depletion layer below the gate electrode 3 and increases the gate-source capacitance Cgs and the minimum noise figure.
Such problems are solved by the device having the following structure. FIG. 11 shows an FET disclosed in the Japanese Patent Publication No. 62-86869 and FIGS. 12(a) to 12(i) show major production process steps therefor. In these figures, reference numeral 1 designates a semi-insulating GaAs substrate, numeral 2 designates an active layer comprising an n-type semiconductor layer, numeral 3 designates a gate electrode, numeral 4 designates a source region, numeral 5 designates a drain region, numeral 6 designates a source electrode, numeral 7 designates a drain electrode, numerals 8, 8', and 8" designate SiO.sub.2 films, numerals 9a and 9b designate photoresists, and numeral 10 designates a Si.sub.3 N.sub.4 film.
The production process will be described.
Silicon ions are implanted into the semi-insulating GaAs substrate 1 by ion implantation and thereafter, annealing is carried out to produce an active layer 2 which will become a channel region (FIG. 12(a)).
Thereafter, a SiO.sub.2 film 8 as a first insulator film is produced on the surface of the active layer 2. A Si.sub.3 N.sub.4 film 10 as a second insulator film is produced on the SiO.sub.2 film 8. Both films 8 and 10 are deposited by a Plasma Vapor Deposition (PVD) method (FIG. 12(b)). In an example, the film thickness of the SiO.sub.2 film 8 is 4000 .ANG., and the film thickness of the Si.sub.3 N.sub.4 film 10 is 1000 .ANG. and the distance l is 2 .mu.m. Silicon ions are implanted with using the SiO.sub.2 film 8 and the Si.sub.3 N.sub.4 film 10 as a mask for selective ion implantation, and annealing in the arsenic ambient is carried out, thereby producing high concentration n-type semiconductor regions as a source region 4 and a drain region 5 (FIG. 12(c)).
Next, the SiO.sub.2 film 8 and the Si.sub.3 N.sub.4 film 10 at the side of the source region 4 are covered by photoresist 9a (FIG. 12(d)), and the SiO.sub.2 film 8 is etched by 0.8 .mu.m from the side of the drain region 5 by a hydrogen fluoride (HF) etchant, thereby producing a SiO.sub.2 film 8' (FIG. 2(e)). Then, the Si.sub.3 N.sub.4 film 10 is not etched.
Thereafter, the photoresist film 9a is removed, the SiO.sub.2 film 8' is again etched by 0.4 .mu.m from the both sides of source and drain region by a hydrogen fluoride (HF) etchant, thereby producing a SiO.sub.2 film 8" of length l' which is equal to 0.4 .mu.m (FIG. 12(f)).
Next, the Si.sub.3 N.sub.4 film 10 is removed, the photoresist 9b is deposited, the surface of the SiO.sub.2 film 8" is exposed, etching the photoresist 9b in an oxygen plasma. Then the SiO.sub.2 film 8" is removed by an HF etchant (FIG. 12(g)).
Thereafter, gate metal is evaporated onto the structure and removed from undesired areas utilizing the photoresist film 9b and the lift-off technique, thereby producing a gate electrode 3 which may be aluminum (FIG. 12(h)).
Ohmic electrodes comprising Au-Ge are produced on the source region 4 and the drain region 5 by conventional photolithography and lift-off techniques to become a source electrode 6 and a drain electrode 7, thereby completing the FET of FIG. 11 (FIG. 12(i)).
As is apparent from FIG. 11, the source region 4 and the drain region 5 are arranged asymmetrically with respect to the gate electrode 3. A predetermined interval is provided between the source region 4 and the gate electrode 2, which results in a high gate to drain breakdown voltage. Furthermore, there is no likelihood that the gate electrode 3 and the source region 4 will be short-circuited as in the prior art examples of FIGS. 7 and 9. The source-gate capacitance Cgs can also be made small, resulting in an FET having a low minimum noise figure.
These prior art production methods for FETs shown in FIGS. 10(a) to 10(f) and FIGS. 12(a) to 12(i) include steps for producing a photoresist film on a gate electrode via an insulator film using photolithography. These steps require precision alignments in the photolithography processes. The precision of alignment needed is generally .+-.0.5 .mu.m. Even if the threshold voltage is determined at a predetermined voltage and the gate length design is previously determined on the basis of that value, the gate length can seldom be produced at the design value. Especially when the gate length is desired to be reduced to about 1 .mu.m for high speed and high frequency properties of, there is the possibility that the gate length will vary within the range of 0.5 to 1.5 .mu.m with the above described alignment precision. Generally, a relationship shown in FIG. 14 is established between the threshold value and the gate length of a transistor. When the gate length is shortened as shown in the drawing, the threshold voltage shifts toward the minus side, thereby producing the short channel effect. This short channel effect is particularly seen when the gate length is below 1 .mu.m, resulting in a problem in the patterning of the gate length.
In the prior art production method for FETs shown in FIGS. 12(a) to 12(i), a gate electrode 3 is produced by defining a configuration of a gate electrode with an insulator film 8" (FIG. 12(f)), plating a photoresist film 9b and removing an SiO.sub.2 film 8" with an HF etchant (FIG. 12(g)), and producing the gate electrode 3 by a lift-off method with utilizing the photoresist 9b as a mask. Accordingly, the gate electrode 3 material must have a melting point such that the photoresist 9b does not degenerate even when the electrode material is vapor plated on the photoresist 9b. Accordingly, Pt (melting point is 1772.degree. C.), Al (melting point is 660.4.degree. C.), or materials having lower melting points are suitable. On the contrary, W or WSi having melting points that are higher than that of Pt cannot be used. WSi.sub.x cannot be used because it is difficult to vapor deposit.
Furthermore, removing SiO.sub.2 film 8" with an HF etchant has inferior controllability due to the high etching rate of the HF etchant.